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of this Bulletin.
Periodically a diffusion engineer will
experience certain difficulties while using the BoronPlus®
or PhosPlus® sources in his/her diffusion system. If this
occurs, it has been our experience that slight modifications
of the current processing parameters and procedures will usually
bring the process back within specifications. With this in
mind, the following table was compiled. It lists some of the
problems that are often experienced by the diffusion engineer,
it outlines the common causes of these problems, and it contains
a number of suggestions that often solve the problems.
Please keep in mind that the information
contained in this bulletin is very general and should only
be used as a guide to troubleshooting a system. If any problem
continues to persist, the process engineer is encouraged to
contact us for additional assistance.
Source Problems
| Problem |
Probable Cause |
Suggested Solution |
Comments* |
| Warpage |
Excessive temp. for
source type |
Use correct
source |
|
Excessive temp.
gradients across sources |
|
|
Source fusing to boat |
(See "Sticking")
Periodically rotate sources within slots |
|
Tight Slots |
See "Sticking" |
|
No silicon between sources |
Always have silicon between sources
during use |
|
| |
|
|
|
Sticking
(look for tiny
pieces of boat
on source or pieces of source on boat) |
Excessive temp. for source type |
Use correct source |
|
Aging sources
too long too high of a temp. |
Follow aging recommendations |
|
Incorrect boat design |
|
|
Excessive B2O3
or P2O5 on
boat and inside slots |
|
|
| |
|
|
|
| Breakage |
Excessive warpage |
Check "warpage" and "sticking"
problems |
|
No silicon between
sources |
Always have silicon
between sources
during use |
|
Thermal shock |
|
|
| |
|
|
|
| Black Spots |
Cutting fluid
in surface imperfections |
Reage in 25-100%
oxygen |
|
1. “Hydrogen Peroxide Solutions
for Silicon Wafer Cleaning”, RCA Engineer, vol. 28-4,
July/Aug 1983, pp. 99-105.
2. Hur-Ling Hsiu, “Effect of Solid
Source Impurities on Silicon Devices”, Thesis at Arizona
State University, Dec. 1988.
3. “Processed-Induced Defects in
Borosilicate Glass-Diffused Silicon”, O. Aina and R.
Kennedy, J. Electrochem. Soc., vol. 131, no. 8, pp 1884-1887.
4. J.E. Rapp, “The Planar Diffusion
Technique”, Semicon Technology Asia 1998/9, Nordica
International. 3.F Block B, Quarry Bay, Hong Kong, p.33.
5. T.A. Carbone, “Solid Source Doping
of a Double Polysilicon Capacitor”, Semiconductor International,
Nov. (1997) p. 89-95.
6. J.E. Rapp and T. A. Carbone, “Surface
Roughness of Polysilicon Layers Doped with Solid Sources”,
Presented at SEMICON® China 99 Technical Symposium, March
17, 1999, Beijing.
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